In a memory, differential signaling is typically used to transmit signals. Differential amplifiers can be used to compare differential inputs against a reference voltage signal to determine the value of a piece of data stored in a memory element, for example. It is therefore, important to have the reference voltage signal at the proper value prior to use. If the reference voltage signal is not at the proper value, then the comparisons made with the differential inputs can result in erroneous assignment of data stored in memory elements.
According to the Joint Electronic Devices Engineering Council (JEDEC) technical standard for double data-rate synchronous dynamic random access memory (DDR SDRAM), inputs to the DDR SDRAM (“memory”), with the exception of a clock enable (CKE) and the main clock signals (CLK,/CLK), are not recognized as being valid until after a reference voltage signal (VREF) is applied. This helps to ensure that VREF has attained the proper value prior to the commencement of operations in the memory. The clock enable, CKE, can initially have a low level (typically between 0.0 v to 0.6 v) and when it transitions to a high level prior the memory beginning operation. Maintaining CKE at the low level ensures that the memory does not begin normal operation until VREF has reached its proper value. However, it is possible to bring CKE to a high level prior to VREF reaching its proper value.
However, it may still be possible begin operation prior to VREF attaining the proper value. For example, a glitch on the VREF signal line may temporarily bring VREF to the proper value and enable the operation of the memory. Since VREF has reached the proper value (albeit for only a short period of time), CKE can transition to a high level. However, by the time the memory begins operations, the glitch has disappeared and VREF is no longer at the proper value.
One prior art method used to address this problem involves the generation of a “CHIP ready” signal once a required power-up command sequence is received. This helps to ensure that even if both VREF and CKE are at their specified values to allow the memory to begin operations, the memory does not start operations until a sequence of commands of specified order is received. While a second prior art method uses a low-voltage CKE receiver, a separate CKE receiver designed to receive a ‘low’ level. The separate CKE receiver can help to eliminate the problem associated with glitches and noise producing erroneous value detections.
One disadvantage of the first prior art method is that the “CHIP ready” signal may be generated accidentally after receiving a random command sequence which may happen to fit the power-up sequence.
A second disadvantage of the first prior art method is that the “CHIP ready” signal can interfere with circuitry in the memory and may result in unwanted and unexpected states.
A disadvantage of the second prior art method is that the DDR SDRAM specifications require a fast detection and does not allow for most kinds of filtering operations that would prevent glitches and/or noise on CKE.